unit testing - SystemVerilog program block vs. traditional testbench -

are there features of sv program block offers can't duplicated other methods?

the less concrete version of question is: should bother program blocks verification? i'm moving environment constrained verilog-95 environment sv supported, , i'm wondering if i'm creating work myself not using program blocks.

check out ieee std 1800-2012 § 3.4 & § 24. full description program blocks.

in short, incomplete summary, program block:

• cannot cannot contain always procedures, primitive instances, module instances, interface instances (virtual interface , port interface allowed), or other program instances.
• specifies scheduling in reactive region. prevents race conditions.
• has system task $exit, terminates program instances calls it.
  • the simulation terminate when program instances have exited.
• is module block except stated above.

the idea of program block create clear separation between test , design. in earlier versions of systemverilog (pre ieee 1800), instantiation of class limited program blocks. emphasized division of test , design. made program blocks vital verification engineers that wanted use object orientated programming in flow. since ieee 1800, class can defined , instantiated anywhere. result, program blocks became less sufficient.

today opinion of usefulness of program block divided. last few conventions been to, trend seems in favor of abandoning program blocks. because advantages can achieved other methods. scheduling in reactive region can done clocking blocks. mailbox, queue([$]), or associative array ([*]) can used intelligently handling simulation terminate running multiple tests. personally, still using program blocks , use initial forever always equivalent when needed. if planning use uvm, non-program blocks test bench might work better you.

in end, comes down methodology preference. best evaluate , try on own.